inforichland/freezing-spice

A pipelined RISCV implementation in VHDL

riscv/riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

PollRobots/scheme

An R7RS Scheme implemented in WebAssembly

LCAI-TIHU/SW

LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V

UlfNorell/x86-agda

Inline, type safe X86-64 assembly programming in Agda

dbp/funtal

FunTAL: mixing a functional language with assembly.

damdoy/ice40_ultraplus_examples

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

garritfra/qbe-rs

QBE IR in natural Rust data structures