lthnh/single-sycle-risc-v-cpu

A RISC-V CPU implementation for learning purposes.

JavaScript

55 commits

updated Aug 31, 2026

See the code

README

Single-Cycle-RISC-V-CPU

A RISC-V CPU implementation for learning purposes. This project strictly uses Verilog IEEE 1364-2005 standard.

Style guide is taken directly from lowRISC at https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md.

Contributors

lthnh

55 commits

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lthnh/single-sycle-risc-v-cpu

A RISC-V CPU implementation for learning purposes.

JavaScript

55 commits

updated Aug 31, 2026

See the code

README

Single-Cycle-RISC-V-CPU

A RISC-V CPU implementation for learning purposes. This project strictly uses Verilog IEEE 1364-2005 standard.

Style guide is taken directly from lowRISC at https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md.

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Contributors

lthnh

55 commits

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JavaScript

71.4%

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Makefile

3.2%