13 repos
freechipsproject/rocket-chip
Rocket Chip Generator
3,862
8,178 commits
chipsalliance/rocket-chip
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
4,778
6,784 commits
ucb-bar/chisel3
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
2,383
5,460 commits
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
2,233
2,364 commits
ucb-bar/firrtl
Flexible Intermediate Representation for RTL
748
2,322 commits
ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
234
398 commits
firesim/FireMarshal
Software workload management tool for RISC-V based SoC research. This is the default workload…
92
515 commits
chipsalliance/chisel-template
A template project for beginning new Chisel work
708
122 commits
ucb-bar/hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
325
726 commits
llvm/circt
Circuit IR Compilers and Tools
2,238
11,898 commits
ucb-bar/gemmini
Berkeley's Spatial Array Generator
1,454
800 commits
