5 repos
olofk/serv
SERV - The SErial RISC-V CPU
1,882
490 commits
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance…
1,691
1,236 commits
rggen/rggen
Code generation tool for control and status registers
470
421 commits
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
1,001
59 commits
keplertech/kepler-formal
Digital Design Equivalence Checking
102
911 commits