Scala-based Hardware Description and RISC-V Design

12 repos

Hardware design and generation tools built primarily in Scala, centered on the Chisel hardware description language and its compiler stack (FIRRTL). This cluster represents a modern approach to RTL design and chip generation, with Chisel and related tools enabling parametric, reusable hardware designs. The repositories include both the core HDL framework and several reference implementations—notably rocket-chip and BOOM—that demonstrate practical application of these tools to RISC-V processor design.

C · 4

Python · 3

Assembly · 2

Scala · 2

Shell · 1

Related clusters

Cluster 44778413 Cluster 4367388 RISC-V Architecture Specifications11 Embedded C Standard Libraries16 Cluster 4378584 Cluster 4378852

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riscv-software-src/riscv-pk

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No description

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riscv/riscv-isa-sim

Spike, a RISC-V ISA Simulator

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riscv-non-isa/riscv-elf-psabi-doc

A RISC-V ELF psABI Document

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852

622 commits

riscv/riscv-elf-psabi-doc

A RISC-V ELF psABI Document

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622 commits

ucb-bar/riscv-torture

RISC-V Torture Test

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222 commits

ucb-bar/berkeley-hardfloat

No description

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193 commits

riscv/riscv-v-spec

Working draft of the proposed RISC-V V vector extension

Assembly

1,089

1,061 commits

riscv/riscv-opcodes

RISC-V Opcodes

Python

874

634 commits