RISC-V Architecture Specifications

11 repos

Specification documents and reference implementations for the RISC-V instruction set architecture and its extensions. These repositories cover core architectural standards (semihosting, supervisor binary interface, fast interrupts, control flow integrity) alongside build tooling and documentation infrastructure. Most repos are specification documents built with Makefile-based workflows, with supporting C and assembly reference implementations.

Makefile · 6

TeX · 3

Assembly · 1

Python · 1

Related clusters

Cluster 4367388 Scala-based Hardware Description and RISC-V Design12 TeX/LaTeX document processing and visualization17 Cluster 4378852 Cluster 43809810 Embedded C Standard Libraries16

riscv/riscv-semihosting-spec

No description

Makefile

94 commits

riscv-non-isa/riscv-semihosting

No description

Makefile

94 commits

riscv-non-isa/riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface

Makefile

482

265 commits

riscv/riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface

Makefile

482

265 commits

riscv/riscv-isa-manual

RISC-V Instruction Set Manual

TeX

4,813

4,470 commits

riscv/integrated-matrix-extension

RISC-V Integrated Matrix Development Repository

TeX

4,275 commits

riscv/riscv-cfi

This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer…

Makefile

650 commits

riscv/riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

Assembly

299

866 commits

riscv/riscv-profiles

RISC-V Architecture Profiles

Makefile

192

305 commits

radisvaliullin/art

Articles

TeX

9 commits

riscv/riscv-code-size-reduction

No description

Python

145

940 commits