8 repos
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
1,038
5,598 commits
chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
394
10,574 commits
MikePopoloski/slang
SystemVerilog compiler and language services
1,141
6,022 commits
google/xls
XLS: Accelerated HW Synthesis
1,896
9,385 commits
YosysHQ/yosys
Yosys Open SYnthesis Suite
4,760
17,556 commits
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at…
3,108
42,240 commits
dalance/sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
482
534 commits
YosysHQ/oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification tools
1,709
855 commits