Cluster 633663

11 repos

Python · 3

C++ · 2

Java · 1

Ruby · 1

SystemVerilog · 1

Assembly · 1

fpga ·16,499

verilog ·14,593

vhdl ·12,701

asic ·8,906

digital-logic ·7,593

digital-logic-design ·7,593

circuits ·7,593

circuit ·7,593

digital-circuits ·7,593

digital-circuit ·7,593

Related clusters

Cluster 6359208 Scala-based Hardware Design and Chip Generation14 Cluster 6390986 Language Server Protocol implementations40 Cluster 63400726 Cluster 63418126

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Haskell

1,615

6,188 commits

rggen/rggen

Code generation tool for control and status registers

Ruby

469

421 commits

olofk/serv

SERV - The SErial RISC-V CPU

Verilog

1,884

490 commits

boldaxolotl/booley

The open-source agentic RTL IDE

Python

1,580 commits

openhwgroup/cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded…

Assembly

3,120

6,544 commits

logisim-evolution/logisim-evolution

Digital logic design tool and simulator

Java

7,593

6,587 commits

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance…

SystemVerilog

1,701

1,236 commits

keplertech/kepler-formal

Digital Design Equivalence Checking

C++

109

911 commits

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Python

227

366 commits

cocotb/cocotb

cocotb: Python-based chip (RTL) verification

Python

2,505

5,249 commits

DegateCommunity/Degate

A modern and open-source cross-platform software for chips reverse engineering.

C++

292

1,107 commits