A Verilog HDL model of the MOS 6502 CPU
See the codeA Verilog HDL version of the old MOS 6502 CPU.
Note: the 6502 core assumes a synchronous memory. This means that valid data (DI) is expected on the cycle after valid address. This allows direct connection to (Xilinx) block RAMs. When using asynchronous memory, I suggest registering the address/control lines for glitchless output signals.
Have fun.
154 followers · starred May 2019
160 followers · starred May 2015
566 followers · starred Oct 2013
250 followers · starred Apr 2021
A Verilog HDL model of the MOS 6502 CPU
See the codeA Verilog HDL version of the old MOS 6502 CPU.
Note: the 6502 core assumes a synchronous memory. This means that valid data (DI) is expected on the cycle after valid address. This allows direct connection to (Xilinx) block RAMs. When using asynchronous memory, I suggest registering the address/control lines for glitchless output signals.
Have fun.
154 followers · starred May 2019
160 followers · starred May 2015
566 followers · starred Oct 2013
250 followers · starred Apr 2021
