MorphCPU

70mm round board, iCE40UP5K on the back and 16 red leds on the front in a 4x4. send it 9 bytes over usb and the grid computes something else

Its like a systolic array basically. no PC no fetch no decode, 16 cells each holding an op and a direction and data goes in the west side and gets mangled by whatever cell it lands on which sounds more complicated than it is. 4 cells from the exit is 4 ticks, thats the bit i like. runs at 4Hz cuz at 16MHz theres obviously nothing to look at

wanted one on a desk so i wrote the fabric. then it needed a testbench, then a board, then a schematic generator cuz i was not drawing 88 symbols by hand, then a placement generator, then a case, and then the case had to be parametric cuz the board diameter kept moving anyway still no traces on it

state

routed. 770 tracks 148 vias across 4 layers, DRC 0 violations, 2 nets still open and theyre both leds so 14 of the 16 light. leaving it there cuz deadline, the board powers and configures and boots and talks. why its two and what would close them is in hardware/ROUTING.md. freerouting got two goes and both went in the bin, the first one ran 211 segments straight across the led face

it needed 4 layers in the end. 2 couldnt do it, the resistor ring and the decap ring both sit inside the F.Cu keepout over the grid so every led escape was stuck on B.Cu alone

no bitstream either. OSS CAD Suite isnt installed on this machine so build.sh has literally never run so idk, salt on the timing numbers

sim 18/18, ERC 0/0, BOM $203.73 for 5

ops

4 bits a cell, 2 op 2 dir, the operand pick is like the only weird bit and morph_cell.v is short enough to just read

        c0    c1    c2    c3
      +-----+-----+-----+-----+
  r0  |  0  |  1  |  2  |  3  |  -> out
      +-----+-----+-----+-----+
  r1  |  4  |  5  |  6  |  7  |  -> out
      +-----+-----+-----+-----+
  r2  |  8  |  9  | 10  | 11  |  -> out
      +-----+-----+-----+-----+
  r3  | 12  | 13  | 14  | 15  |  -> out
      +-----+-----+-----+-----+
         ^
      data in

east edge comes back over uart. everything else just falls off the board. five commands total and gateware/README.md has the actual bytes plus a worked example

parts

two regulators, and the 1v2 one has to be up before the 3v3, which is backwards from the cascade youd reach for first. i would not wing that bit, hardware/DESIGN.md has it with page numbers, money is in docs/BOM.md

run

cd gateware/sim && ./run_sims.sh    # iverilog only
cd gateware && ./build.sh           # needs OSS CAD Suite. never run.
cd case && ./export.sh

pics

75.4mm, 12.9g, like 26c of PLA

front. 4x4 on 9mm pitch plus the reset button and the CDONE led. no tracks on this face on purpose, theres an F.Cu keepout over the whole grid

back. fpga in the middle, ring of decaps then the resistor ring, and everything fanning out of a QFN-48 on 0.5mm pitch which is where all the pain was

board was 60mm at first and everything overlapped. the resistor ring also sat 180 out from its own leds for ages, so every single anode trace ran straight under the QFN paddle, which took embarrassingly long to spot, rip. both sorted

six leds also ended up on different fpga pins than they started on, cuz the east side of the package ran out of escape room. thats in ROUTING.md too

if you order it

gerbers in hardware/fab_output/ are off the routed board now, all four copper layers with copper actually in them, drill included. two nets are still open tho so D2 and D3 wont light, read that before you spend money

• $203.73 is a real 4 layer quote. $6.27 of headroom under the $210 Complex cap, so dont add parts casually. re-quote if the BOM moves
• fpga stock was 546 when i looked. oscillator 147
• C7519 and C136491 tiers are guesses, confirm in the quote
• QFN paddle is the only ground to the die, SG48 has no GND pin at all. window the paste stencil

case prints flat, no supports, 0.2mm layers, 3 perimeters

licence

apache 2.0