A simple superscalar out-of-order RISC-V microprocessor
SystemVerilog
255
494 commits
updated Feb 24, 2025
SoomRV is a simple superscalar out-of-order RISC-V core able to execute up to 4 instructions per cycle and capable of booting Linux. Check the latest CI logs to see a Linux boot log!
For running SoomRV on FPGA, have a look at the SoomRV-Arty Repo.
strcmp Execution (visualized using Konata)
make setup to build submodules.make to build a binary with Verilator (alternatively, make trace will also generate VCD traces)../obj_dir/VTop <assembly file> or <baremetal elf file>.
For example, run ./obj_dir/VTop test_programs/dhry_1.s to run Dhrystone. Optionally add --perfc to print out perf counters, or -x <start_time> to specify when to enable tracing (-x0 for tracing from start)../obj_dir/VTop --perfc --device-tree=test_programs/linux/device_tree.dtb test_programs/linux/linux_image.elf (or make linux for a full build). Log in as root, no password.
Building Linux and booting it in simulation takes at least a few hours!The console input is line-buffered for easier input at low simulation speed. Within Linux, you will thus see all input lines twice.
While running, the simulator will save its state about once a minute if
--backup-file=<NAME>.backup is specified. Simulation can then be restarted
at the backup by running ./obj_dir/VTop <NAME>.backup. The file name must
end with .backup. If cosim is enabled, a matching .backup_cosim file will
be written/read as well.
This is on by default for make linux. To restart a crashed or closed Linux boot
at the last checkpoint, use e.g. ./obj_dir/VTop soomrv.backup --backup-file=soomrv2.backup.
(There seem to be some spurious segfaults in the Verilator-generated code.)
For a general overview of the implementation, see Overview.
SoomRV is released under the MIT License. Use of this source code is governed by a MIT-style license that can be found in the LICENSE file.
riscv-isa-sim (aka Spike): released under the 3-Clause BSD License, used in conjunction with the simulator.hardfloat: released under the 3-Clause BSD License.SystemVerilog
45.0%
Assembly
27.1%
C++
14.7%
Verilog
9.1%
C
3.3%
A simple superscalar out-of-order RISC-V microprocessor
SystemVerilog
255
494 commits
updated Feb 24, 2025
SoomRV is a simple superscalar out-of-order RISC-V core able to execute up to 4 instructions per cycle and capable of booting Linux. Check the latest CI logs to see a Linux boot log!
For running SoomRV on FPGA, have a look at the SoomRV-Arty Repo.
strcmp Execution (visualized using Konata)
make setup to build submodules.make to build a binary with Verilator (alternatively, make trace will also generate VCD traces)../obj_dir/VTop <assembly file> or <baremetal elf file>.
For example, run ./obj_dir/VTop test_programs/dhry_1.s to run Dhrystone. Optionally add --perfc to print out perf counters, or -x <start_time> to specify when to enable tracing (-x0 for tracing from start)../obj_dir/VTop --perfc --device-tree=test_programs/linux/device_tree.dtb test_programs/linux/linux_image.elf (or make linux for a full build). Log in as root, no password.
Building Linux and booting it in simulation takes at least a few hours!The console input is line-buffered for easier input at low simulation speed. Within Linux, you will thus see all input lines twice.
While running, the simulator will save its state about once a minute if
--backup-file=<NAME>.backup is specified. Simulation can then be restarted
at the backup by running ./obj_dir/VTop <NAME>.backup. The file name must
end with .backup. If cosim is enabled, a matching .backup_cosim file will
be written/read as well.
This is on by default for make linux. To restart a crashed or closed Linux boot
at the last checkpoint, use e.g. ./obj_dir/VTop soomrv.backup --backup-file=soomrv2.backup.
(There seem to be some spurious segfaults in the Verilator-generated code.)
For a general overview of the implementation, see Overview.
SoomRV is released under the MIT License. Use of this source code is governed by a MIT-style license that can be found in the LICENSE file.
riscv-isa-sim (aka Spike): released under the 3-Clause BSD License, used in conjunction with the simulator.hardfloat: released under the 3-Clause BSD License.SystemVerilog
45.0%
Assembly
27.1%
C++
14.7%
Verilog
9.1%
C
3.3%