NeXTBus Raspberry Pi PCB Prototype

NeXTbus-to-Raspberry-Pi hardware exploration.

The project now has a separate Rev1 functional-card specification for a slave-only FPGA target with a Raspberry Pi Compute Module control node and optional worker modules. The intended service path begins with virtual SCSI and diagnostic shared memory, then can expand toward graphics acceleration and NeXTdimension research.

The current board is Rev0.4: a passive monitor/breakout and development-matrix adapter. It is not an active Raspberry Pi interface yet, and the Pi headers are intentionally isolated. The immediate goal is to verify connector orientation, power rails, clock/reset behavior, slot ID pins, and NeXTbus-specific signal differences before designing an FPGA/CPLD target card.

The PCB now uses the full NBIC breadboard envelope from the fabrication drawing, 10.643 x 10.160 in, with the original 0.073 in +/- 0.006 in finished board thickness and a 4-layer stackup. J11 is placed on the presumed backplane edge. Rear I/O fence openings, ejector/retainer features, and exact connector insertion depth still need physical verification before production.

Rev0.4 Board

Rev0.4 contains:

• 96-pin DIN 41612 NeXTbus connector footprint.
• Two isolated Raspberry Pi 2x20 headers: control and worker/service expansion.
• 96 through-hole test pads, one per NeXTbus pin.
• Short direct traces from each connector pin to its matching test pad.
• NBIC-breadboard-derived signal labels, with ambiguous pins marked VERIFY_*.
• Full-size board outline matching the available NeXT fab drawing.
• 4-layer / 0.073 inch board construction matching the fab drawing callouts.
• A stepped development matrix: 1760 holes on the original-style 0.100 inch grid, with the lower-left area reserved for bus-interface circuitry.
• Five-hole coordinate legends and A-H section marks rendered as exposed front copper through matching solder-mask openings.
• Native vector NeXT cube artwork generated from NeXT_logo.svg on front silkscreen.

The current connector map is no longer a generic NuBus placeholder. It is derived from NBIC_Breadboard_Schematic.pdf page 2, connector J11, where legible. Row B is the GAD0 through GAD31 bus, row A contains control/arbitration/clock/reset/power-control signals, and row C still has several VERIFY_* power/ground entries that need bench confirmation.

NBIC-side signal naming from the same schematic:

Source Material

The original PDF is a scanned fabrication drawing, not reusable CAD artwork. It does not contain recoverable Gerbers, Excellon drill data, copper geometry, or a netlist.

Board-area detail:

Notes

• Do not connect NeXTbus directly to Raspberry Pi GPIO.
• Treat NeXTbus pins as 5 V TTL until measured.
• Use Rev0.4 only for passive probing, prototyping, and pinout verification.
• See NEXTBUS_PI_ADAPTER.md, REV0_MONITOR_BOARD.md, and nextbus_nubus_reference_pinout.csv for the working design notes.
• The generated Rev0.4 netlist is only connector-to-test-point continuity. Matrix holes and Pi headers are intentionally unconnected; a functional card requires a schematic-driven Rev1 netlist.

KiCad MCP Server and Codex 5.5 medium on the first pass.