New Chadrock v2 llama.cpp and config!

Chadrock-35B Ace Saber ROCmFP4 MTP + ROCmFPX MoEQuality

Chadrock-35B Ace Saber is a local AMD Strix Halo release with two additive serving lanes: the original ROCmFP4/MTP speed lane, and a new ROCmFPX MoEQuality-7.07 BPW lane for quality-sensitive coding and agent work. The original lane remains here unchanged; the FPX file is added as a second downloadable GGUF.

This release also includes a tested Qwen3.6 vision projector, so the same full Chadrock language GGUF can run image-text prompts when launched with --mmproj.

The model behavior comes from the Ace Saber build by @DJLougen. The published measurements below use the Chadrock v2 ROCmFPX llama.cpp runner family from ciru-ai/ROCmFPX, with the exact ROCmFP4 and ROCmFPX runner references listed in the settings section.

These GGUFs will not run correctly with stock llama.cpp. Use the Chadrock v2 ROCmFPX runner because these files use ROCmFP4/ROCmFPX tensor types and MTP serving controls that upstream llama.cpp does not currently understand.

The model files are already provided here. You do not need to rebuild or quantize the model.

Why This Mix

Ace Saber gives the model its coding, agentic, and tool-use behavior. Chadrock/ROCmFP4 gives it the speed profile needed to feel good locally on AMD unified-memory hardware.

The goal is not just another Qwen3.6 quant. The goal is:

• Ace Saber behavior from @DJLougen
• Qwen3.6 35B-A3B MoE efficiency
• MTP speculative decoding
• ROCmFP4 tensor-aware quantization
• ROCmFPX MoEQuality-7.07 BPW for the additive ultra-quality lane
• high-throughput local serving on Ryzen AI Max+ 395 / Strix Halo

Technical Metadata

Hugging Face may round the parsed GGUF tensor count to 36B in its automatic badge. This release is the Qwen3.6 35B-A3B MoE family: about 35B-class total parameters with roughly 3B active parameters per token.

Vision Support

Vision is provided by mmproj-CHADROCK-35B-Ace-Saber-F32.mmproj, a GGUF-format Qwen3VL projector converted from the restored Qwen3.6 visual tower sidecar in the upstream Ace Saber release.

This does not replace the language model and does not disable MTP. The validated command used the full Chadrock ROCmFP4 GGUF with native --spec-type draft-mtp enabled and added the projector with --mmproj.

Local validation used two generated images whose answers were not present in the prompt:

The same gate fails without a projector, so this is a real image-read check rather than a metadata-only claim.

Release Lanes

ROCmFPX MoEQuality-7.07 BPW Lane

The new FPX lane was built as a quality-focused MoE recipe for the same ACE/SABER 35B-A3B MTP model. The full quantization log reports the 753-tensor qwen35moe topology at 29945.07 MiB (7.07 BPW).

Best local task-eval profile for this lane is Vulkan, one slot, prompt cache disabled, deterministic sampling, MTP on, f16 draft KV, and the current draft cap profile described below.

Quality Metrics

Useful local comparisons:

Speed Metrics

The tuned Vulkan cap2 profile uses f16 target KV, f16 draft KV, speculative.n_max=2, p_min=0.25, p_split=0.10, gen512, and prompt cache disabled:

Matched 8k/gen512 comparison against stock Unsloth Qwen3.6 35B Q6 K XL, same prompt, Vulkan, f16 target/draft KV, MTP on, n_max=2, and deterministic sampling:

On that matched row, the FPX quality lane is 8.0% faster on decode (69.55 vs 64.39 tok/s), while Q6 keeps a prefill and TTFP edge and the short 512-token wall time is nearly tied.

The first backend sweep for the FPX lane used cap4, n_max=4, and f16 target/draft KV. Vulkan was the better serving path for decode and draft acceptance:

Chadrock v2 Speed

Best current text-only profile on AMD Ryzen AI Max+ 395 / Strix Halo: pinned Chadrock v2 ROCmFPX llama.cpp, Vulkan0 target plus Vulkan0 draft, f16/f16 target and draft KV, one slot, prompt cache disabled, no multimodal projector, deterministic decoding, and request policy speculative.n_max=4, speculative.n_min=0, speculative.p_min=0.25.

Against the same-run no-draft control, the new Chadrock v2 MTP config is 1.97x faster in decode at both gen512 and gen2048: 143.08 vs 72.57 tok/s, and 141.77 vs 72.04 tok/s.

Compared with the older Chadrock v1 card-speed profile (~101.31 tok/s aggregate HumanEval eval speed), the new best served text row is about 1.41x faster (+41.2%). Compared with the older uncached Chadrock TG64 served row (78.28 tok/s server eval), the new gen2048 row is about 1.81x faster (+81.1%). Those older rows are not identical prompts, so treat them as release-to-release runner evidence rather than a strict apples-to-apples benchmark pair.

The older 2026-06-07 HumanEval rerun is still useful as a quality guard: it generated 48,824 completion tokens across 164 tasks at ~101.31 tok/s aggregate llama-server eval speed and produced the 155/164 base pass@1 and 148/164 HumanEval+ pass@1 result below.

HumanEval

This model also posts an exceptional HumanEval result for a local GGUF run:

The fresh 32k rerun still beats the recorded stock 27B row on base HumanEval, while the older row remains one task higher on HumanEval+.

BigCodeBench-Hard

The same tuned Chadrock Vulkan d2 family was also run on BigCodeBench-Hard-Instruct:

This is a harder instruction-coding benchmark than HumanEval and is included as a sanity check that the speed-tuned runtime still produces usable code under a broader task mix.

Best Settings / Advanced Setup

For runner build commands, request-level speculative controls, and the 35B/27B reproduction notes, use the advanced Ciru setup page:

https://llm.ciru.ai/chadrock-rocmfpx/

Runner references used for the published rows:

ROCmFP4 speed lane: ciru-ai/ROCmFPX commit 7aa484a2f0a504dc612a3d74a068024f3e6d6353
ROCmFPX MoEQuality lane: ciru-ai/ROCmFPX branch ciru-ai/fp6-vulkan-dequant-speed, commit fd6555ffb36dcef6419757189012c8c4fd31f91f

Recommended build for current serving: ciru-ai/ROCmFPX main commit 647fd52965a401d7fa8e035fc76a16c94216a794.

For the fastest measured text-only ACE/SABER path on Strix Halo, use:

backend: Vulkan0 target + Vulkan0 draft
context: 32768
batch / ubatch: 2048 / 512
target KV: f16 / f16
draft KV: f16 / f16
MTP: draft-mtp, n_max=4, n_min=0, p_min=0.25, p_split=0.10
serving: one slot, prompt cache disabled for benchmarks, --no-mmproj for text speed
sampler: temperature=0, top_p=0.95, top_k=20

That is the profile that produced 143.08 tok/s at gen512 and repeated at 141.77 tok/s at gen2048 on the 3946-token text prompt. For image-text use, remove --no-mmproj and add --mmproj mmproj-CHADROCK-35B-Ace-Saber-F32.mmproj; the headline speed row above is text-only.

For the new FPX quality lane, the current general Strix profile is:

backend: Vulkan0 target + Vulkan0 draft
context: 262144
batch / ubatch: 2048 / 512
target KV: f16 / f16
draft KV: f16 / f16
MTP: draft-mtp, n_max=4 for vision/general use; n_max=2 for the tuned speed row
serving: one slot, prompt cache disabled for benchmarks
sampler: temperature=0, top_p=0.95, top_k=20

The HermesAgent-20 quality row used the text-only 64k task-eval variant: q8_0/q8_0 target KV, f16/f16 draft KV, no projector, and n_max=3.

Run With llama-server

Build the Chadrock v2 ROCmFPX llama.cpp runner once, download the GGUF lane you want, then run from the ROCmFPX checkout.

For the new ROCmFPX MoEQuality lane:

./build-strix-rocmfp4/bin/llama-server \
  -m /path/to/CHADROCK-35B-Ace-Saber-MTP-ROCmFPX-MoEQuality-7.07BPW.gguf \
  --alias chadrock-35b-ace-saber-rocmfpx-moequality-707bpw-cap4 \
  --host 127.0.0.1 \
  --port 18180 \
  --jinja \
  -c 262144 \
  --reasoning off \
  --reasoning-format none \
  --reasoning-budget -1 \
  --no-context-shift \
  -dev Vulkan0 \
  -ngl 999 \
  -fa on \
  -b 2048 \
  -ub 512 \
  -t 16 \
  -tb 32 \
  -ctk f16 \
  -ctv f16 \
  --temp 0 \
  --top-p 0.95 \
  --top-k 20 \
  --seed 123 \
  --parallel 1 \
  --mmproj /path/to/mmproj-CHADROCK-35B-Ace-Saber-F32.mmproj \
  --metrics \
  --no-webui \
  --cache-ram 8192 \
  --ctx-checkpoints 32 \
  --checkpoint-every-n-tokens 8192 \
  --spec-type draft-mtp \
  --spec-draft-device Vulkan0 \
  --spec-draft-ngl all \
  --spec-draft-threads 16 \
  --spec-draft-threads-batch 32 \
  --spec-draft-type-k f16 \
  --spec-draft-type-v f16 \
  --spec-draft-n-max 4 \
  --spec-draft-n-min 0 \
  --spec-draft-p-min 0.25 \
  --spec-draft-p-split 0.10 \
  --no-spec-draft-backend-sampling \
  --spec-draft-poll 1 \
  --spec-draft-poll-batch 1

For the tuned text-only speed row, use the same FPX command with --no-mmproj, --spec-draft-n-max 2, and the same f16 target/draft KV shown above. For the HermesAgent-20 quality row, use -c 65536, --no-mmproj, -ctk q8_0, -ctv q8_0, and --spec-draft-n-max 3.

For the original ROCmFP4 speed lane:

./build-strix-rocmfp4/bin/llama-server \
  -m /path/to/Qwen3.6-35B-A3B-NSC-ACE-SABER-MTP-F16-to-ROCmFP4-STRIX_LEAN.gguf \
  --alias chadrock-35b-ace-saber-rocmfp4-cap4 \
  --host 127.0.0.1 \
  --port 18180 \
  --jinja \
  -c 32768 \
  --reasoning off \
  --reasoning-format none \
  --reasoning-budget -1 \
  --no-context-shift \
  -dev Vulkan0 \
  -ngl 999 \
  -fa on \
  -b 2048 \
  -ub 512 \
  -t 16 \
  -tb 32 \
  -ctk f16 \
  -ctv f16 \
  --temp 0 \
  --top-p 0.95 \
  --top-k 20 \
  --seed 123 \
  --parallel 1 \
  --no-mmproj \
  --metrics \
  --no-webui \
  --cache-ram 8192 \
  --ctx-checkpoints 0 \
  --checkpoint-every-n-tokens -1 \
  --spec-type draft-mtp \
  --spec-draft-device Vulkan0 \
  --spec-draft-ngl all \
  --spec-draft-threads 16 \
  --spec-draft-threads-batch 32 \
  --spec-draft-type-k f16 \
  --spec-draft-type-v f16 \
  --spec-draft-n-max 4 \
  --spec-draft-n-min 0 \
  --spec-draft-p-min 0.25 \
  --spec-draft-p-split 0.10 \
  --no-spec-draft-backend-sampling \
  --spec-draft-poll 1 \
  --spec-draft-poll-batch 1

Use --parallel 1 for MTP. Multi-slot serving changes the MTP behavior and is not the intended profile. The benchmark table above used -c 32768 and --no-mmproj for the fastest text row. For image-text use, remove --no-mmproj and add the projector:

--mmproj /path/to/mmproj-CHADROCK-35B-Ace-Saber-F32.mmproj

For general local coding and agent work, you can raise context after validating memory headroom on your machine. The advanced page below keeps the copy-paste build and launch blocks current:

https://llm.ciru.ai/chadrock-rocmfpx/

About Ace Saber

The source checkpoint is GestaltLabs/Qwen3.6-35B-A3B-NSC-ACE-SABER, based on Qwen/Qwen3.6-35B-A3B. The direct GGUF-MTP source is GestaltLabs/Qwen3.6-35B-A3B-NSC-ACE-SABER-GGUF-MTP.

Training order:

Qwen3.6-35B-A3B -> NSC-ACE -> SABER

NSC-ACE uses multiple steered rollouts from the same model and rewards convergence across latent behavior modes, especially for tool-call structure, reasoning wrappers, self-consistency, and avoiding repeated loops.

SABER is the final calibration pass. The source model card reports 98.33% HarmBench-300 compliance and final KLD 0.025383937664711.

About Chadrock / ROCmFP4 / ROCmFPX

Chadrock v2 uses the Ciru ROCmFPX llama.cpp branches carrying the ROCmFP4 and ROCmFPX tensor/runtime work plus request-level MTP serving controls.

ROCmFP4 is not stock Q4, MXFP4, or NVFP4. It uses custom Codebook10 4-bit weights, finite unsigned E4M3 scale semantics, tensor-aware presets, ROCm/HIP kernels, Vulkan shader support, and MTP regression guards.

ROCmFPX is the higher-bit experimental family used for the new MoEQuality lane. In this release it is applied as a tensor-aware 7.07 BPW quality recipe for the 35B-A3B MoE topology.

Why it matters: Ryzen AI Max+ 395 / Strix Halo has a large unified-memory pool, but decode speed still depends heavily on bandwidth, tensor layout, and draft-token acceptance. ROCmFP4 is designed to make this class of AMD machine fast enough for serious local long-context use, while the FPX lane gives a quality-first option on the same card.

Build The Required llama.cpp

The GGUF files are already provided. You only need to build the custom llama.cpp server once:

git clone https://github.com/ciru-ai/ROCmFPX.git
cd ROCmFPX
git checkout 647fd52965a401d7fa8e035fc76a16c94216a794
env JOBS=16 scripts/build-strix-rocmfp4-mtp.sh llama-server llama-bench

The 262K serving profile keeps 32 context checkpoints at 8192-token intervals so long prompts can reuse cached work across the configured context. The pinned runner includes the MTP checkpoint-storage and restore-safety fixes required for this profile.

The server binary will be here:

build-strix-rocmfp4/bin/llama-server

Files

Credits

• @DJLougen: Ace Saber / NSC-ACE SABER model build.
• Ciru / ciru-ai/ROCmFPX: Chadrock v2 ROCmFPX llama.cpp runner, ROCmFP4 and ROCmFPX tensor/runtime work, build path, request-level MTP controls, and public reproduction page.
• charlie12345 / @Italianclownz: original ROCmFP4 direction and AMD-focused runtime work that informed the Chadrock path.
• Qwen: base Qwen3.6-35B-A3B model.

Notes

This is an experimental AMD ROCmFP4/ROCmFPX/MTP release. Performance depends on driver version, clocks, prompt shape, MTP acceptance, and serving flags. The numbers above are local reproducible measurements, not universal llama.cpp claims.