5 repos
pratheekmotamarri/llm-verilog-testbenchgen
Generating Verilog Testbenches using LLM
0
2 commits
Anjiang-Wei/VeriCoder
No description
15
8 commits
avanig1834/LLM-VeriBench
Large Language Model-powered Verilog Testbench Generator
1
10 commits
NVlabs/verilog-eval
Verilog evaluation benchmark for large language model
472
12 commits
shailja-thakur/AutoChip
62
58 commits
