🧠⚡ Awesome AI for Chip Design

A curated, community-maintained list of ML/LLM research & tools across the chip-design flow — from specification to silicon.

Artificial intelligence — large language models in particular — is reshaping how chips are designed, verified, and optimized. This list tracks research and open tools that apply ML/LLMs across the chip-design flow: specification and high-level synthesis, RTL generation, verification and debug, logic and physical synthesis, PPA optimization, analog and mixed-signal, FPGA, testing, and hardware security — plus the foundation models, benchmarks, datasets, techniques, and multi-agent frameworks that underpin them.

Inclusion does not imply endorsement; categories are best-effort and subjective — please open an issue or PR to correct them.

📊 At a glance

📅 Papers by year

xychart-beta
    title "Papers by year"
    x-axis [2023, 2024, 2025, 2026]
    y-axis "count" 0 --> 220
    bar [17, 110, 211, 158]

🥧 Listed entries by category (top 9 + others)

pie title "Listed entries"
    "RTL Generation" : 107
    "Verification" : 80
    "Multi-Agent" : 56
    "Techniques" : 41
    "Analog/MS" : 32
    "Benchmarks" : 26
    "Foundation" : 21
    "HLS" : 21
    "Security" : 20
    "Others" : 97

Contents

• 🧱 Front-end Design
  • 📋 Specification & System-Level
  • ⚙️ High-Level Synthesis
  • 🔣 RTL Generation
  • ✅ Verification & Testbench
  • 🐛 Bug Fixing & Debug
• 🏗️ Back-end Design
  • 🔀 Logic Synthesis
  • 📐 Physical Design & PPA
• 🌐 Domains
  • 📡 Analog & Mixed-Signal
  • 🧩 FPGA
  • 🔒 Hardware Security
  • ⚡ AI Accelerator & Architecture
• 🏛️ Foundations & Infrastructure
  • 🧠 Foundation Models
  • 🗂️ Benchmarks & Datasets
  • 🛠️ Techniques (RAG/RL/Prompt/FT)
  • 🤖 Multi-Agent Systems
  • 🛰️ EDA Tools & Copilots
• 📚 Surveys & Reviews

🧱 Front-end Design

📋 Specification & System-Level

• AGON: Automated Design Framework for Customizing Processors from ISA Documents - (2024).
• Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? - (2024).
• HWE-Bench: Can Language Models Perform Board-level Schematic Designs? - (2026).
• PCBSchemaGen: Constraint-Guided Schematic Design via LLM for Printed Circuit Boards (PCB) - (2026).
• SchGen: PCB Schematic Generation with Semantic-Grounded Code Representations - (2026).

⚙️ High-Level Synthesis

• A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks - (2025).
• Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024) - (2024).
• Are LLMs Any Good for High-Level Synthesis? - (2024).
• AutoBeaVer: Automating Behavioral Modeling and Verification in Library Characterization with LLM Agents - (2026).
• Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation - (2026).
• Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective - (2025).
• ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis - (2025).
• CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference - (2025).
• Dataset for LLM-Driven C-to-HLS Hardware Code Synthesis - (2025).
• DiffHLS: Differential Learning for High-Level Synthesis QoR Prediction with GNNs and LLM Code Embeddings - (2026).
• Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis - (2024).
• From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis - (2026).
• HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks - (2025).
• HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis - (2025).
• Iceberg: Enhancing HLS Modeling with Synthetic Data - (2025).
• Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models - (2025).
• LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning - (2025).
• LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization - (2025).
• LLM-Driven C-to-Verilog Translation via HLS with Automated Verification - (2026).
• Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models - (2024).
• Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation - (2025).

🔣 RTL Generation

• A Code Translation Dataset for Enhanced LLM Verilog Generation - (2025).
• A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation - (2023).
• A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization - (2025).
• A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base - (2025).
• A Multi-Expert Large Language Model Architecture for Verilog Code Generation - (2024).
• A New Benchmark for the Appropriate Evaluation of RTL Code Optimization - (2026).
• A Systematic Framework for Automated Verilog Code Generation using LLMs - (2024).
• Advanced Large Language Model (LLM)-Driven Verilog Development - (2023).
• Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric - (2025).
• AI-Driven RTL Generation with Verification In-The-Loop - (2024).
• An Evolutionary Framework for RTL Generation driven by Large Language Models - (2025).
• An Iterative Framework for Fine-tuning LLMs for RTL Code Generation - (2024).
• Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback - (2024).
• Autonomous Verilog Coding Agents with Graph-based Planning and AST-based Waveform Tracing - (2024).
• Autosilicon: Scaling up rtl design generation capability of large language models - (2025).
• AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning - (2026).
• Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning - (2026).
• Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization - (2025).
• ChatCPU: An Agile CPU Design and Verification Platform with LLM - (2024).
• ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration - (2026).
• ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation - (2026).
• Classification-Based Automatic HDL Code Generation Using LLMs - (2024).
• Closing the Loop in LLM-Based Hardware Generation: An Autonomous Agentic Workflow for Robust TPU Design - (2026).
• CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization - (2024).
• COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation - (2026).
• Controlled Verilog Generation with Discriminative Guidance - (2024).
• CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation - (2024).
• Correct and Compositional Hardware Generators - (2024).
• DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs - (2025).
• DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis - (2025).
• Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form - (2025).
• Digital ASIC Design with Ongoing LLMs - (2024).
• EDA-Aware RTL Generation with Large Language Models - (2024).
• Effective Automatic Chisel Code Generation by LLM with Reflection - (2025).
• Empowering LLMs for Verilog Generation through Multi-Level Summarization - (2024).
• Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation - (2025).
• Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection - (2024).
• Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation - (2025).
• Evaluating Creativity of LLM-Based Hardware Code Generation - (2024).
• Evaluating Large Language Models for Verilog Code Generation - (2023).
• Evolutionary Search for LLM-based Verilog Generation and Optimization - (2026).
• EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code - (2025).
• Exploiting Information Locality for IP-level Verilog Generation - (2026).
• Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation - (2026).
• Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware - (2025).
• FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design - (2025).
• Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique - (2023).
• Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning - (2025).
• Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers - (2025).
• HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL - (2025).
• HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design - (2024).
• Hivegen–hierarchical llm-based verilog generation for scalable chip design - (2025).
• How far are we from natural language hardware design - (2023).
• HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design - (2026).
• Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation - (2026).
• IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution - (2026).
• Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement - (2026).
• Large Language Model for Verilog Code Generation - (2025).
• Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning - (2024).
• LLM Unlearning for Reliable Hardware Code Generation - (2025).
• LLM-based Behaviour Driven Development for Hardware Design - (2025).
• LLM-based High-Quality RTL Code Generation Using MCTS - (2024).
• LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation - (2026).
• LLM4RTL: Tool-Assisted LLM for RTL Generation - (2026).
• Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation - (2024).
• Natural Language Exploration of Hardware Designs and Libraries - (2024).
• Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation - (2024).
• NotSoTiny: A Large, Living Benchmark for RTL Code Generation - (2025).
• Open Dataset and Benchmark for LLM-Aided Design RTL Generation - (2025).
• OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design - (2025).
• Paradigm-Based Automatic HDL Code Generation Using LLMs - (2025).
• Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models - (2025).
• PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs - (2025).
• ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols - (2025).
• Python-based DSL for generating Verilog model of Synchronous Digital Circuits - (2024).
• QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation - (2025).
• QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design - (2025).
• QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation - (2025).
• RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs - (2025).
• ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards - (2025).
• RTL++: Graph-enhanced LLM for RTL Code Generation - (2025).
• RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision - (2026).
• RTL-Forge: CNF-Anchored, LLM-Assisted Verilog Generation - (2026).
• Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems - (2025).
• Survey and Benchmarking of Large Language Models for RTL Code Generation: Techniques and Open Challenges - (2025).
• SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning - (2025).
• Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation - (2025).
• Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation - (2026).
• The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation - (2025).
• Towards llm-powered verilog rtl assistant: Self-verification and self-correction - (2024).
• TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator - (2025).
• Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development - (2025).
• VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination - (2025).
• VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization - (2025).
• VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs - (2026).
• VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding - (2025).
• Veriloc: Line-of-code level prediction of hardware design quality from verilog code - (2026).
• Verilog Code Generation of Hierarchical Design Using LLMs - (2025).
• Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation - (2026).
• VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation - (2026).
• VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs - (2025).
• VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation - (2025).
• VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation - (2025).
• VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning - (2025).
• Vgv: Verilog generation using visual capabilities of multi-modal large language models - (2024).
• VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation - (2024).
• VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency - (2025).

✅ Verification & Testbench

• (Security) Assertions by Large Language Models - (2023).
• A Large Language Model for Solving Assertion Failures in RTL Design - (2025).
• A LoRA Fine-Tuned LLM Model for Efficient Automated Assertion Generation - (2025).
• A Multi-Agent Generative AI Framework for IC Module-Level Verification Automation - (2025).
• A Retrieval-Augmented Framework for Automated RTL Testability Repair - (2025).
• AI-Assisted Hardware Security Verification - (2026).
• AI-Driven RTL Generation with Verification In-The-Loop - (2024).
• An AST-guided LLM Approach for SVRF Code Synthesis - (2025).
• an Automated LLM-aided UVM Machine for RTL Verification - (2025).
• an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification - (2026).
• An Automated Universal RTL Verification Framework using LLMs - (2024).
• An Efficient Program Generation Multi-Agent System for Automatic RTL Verification - (2025).
• Analogtester: A large language model-based framework for automatic testbench generation in analog circuit design - (2025).
• Architect in the Loop Agentic Hardware Design and Verification - (2025).
• Are LLMs Ready for Practical Adoption for Assertion Generation? - (2025).
• Assertain: Automated Security Assertion Generation Using Large Language Models - (2026).
• AssertFix: Empowering Automated Assertion Fix via Large Language Models - (2025).
• AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging - (2025).
• AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generation - (2024).
• AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL - (2025).
• Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms - (2024).
• Automated RTL Design with Backtrack-ToT - (2025).
• Automated SVA Generation with LLMs - (2026).
• Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting - (2024).
• Automatic Testbench Generation and Evaluation Using LLMs for HDL Design - (2024).
• Automatic TestBench Generation for Digital Design in the Era of AI - (2026).
• Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework - (2025).
• Automation of LLM Self-Instructing for Hardware Security Verification - (2024).
• Bridging RTL and Assertion Generation with Large Language Models - (2026).
• Can LLMs Design Real Hardware? A New Benchmark for RTL Design and Verification Tasks - (2024).
• Can LLMs do Induction Proofs for Hardware? - (2025).
• ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs - (2026).
• Chattest: Coverage-enhanced testbench generation for agile hardware verification with llms - (2026).
• ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation - (2024).
• ConfiBench: Automatic Testbench Generation with Confidence-Based Scenario Mask and Testbench Ensemble using LLMs for HDL Design - (2026).
• CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design - (2024).
• CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations - (2026).
• DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specifications - (2025).
• EDA-in-the-Loop: Automated HDL Code Generation and Verification Using Multi-Agent LLMs - (2025).
• Embedded Tutorial: AI Vs. Verification Engineer: Fight or Synergy? - (2026).
• Enhancing Large Language Models for Hardware Verification - (2025).
• Exploring Agentic LLM Paradigms for Hardware Verification across Abstraction Levels - (2026).
• From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation - (2026).
• From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation - (2026).
• FVRuleLearner: Operator-Level Reasoning Tree (OP-Tree)-Based Rules Learning for Formal Verification - (2026).
• GenAI through the Lens of Formal Verification - (2024).
• Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs - (2024).
• Hardware Design and Verification with Large Language Models: A Literature Survey, Challenges, and Open Issues - (2025).
• HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs - (2026).
• HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL - (2025).
• Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification - (2025).
• HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification - (2026).
• Improving LLM-Based Hardware Test Plan Generation - (2026).
• Intermediate Representations for LLM-Based Test Generation: A Comparative Study in Automotive Software Verification - (2026).
• Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification - (2026).
• Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification - (2026).
• LLM Assisted Assertion Generation for RTL Design Verification - (2024).
• LLM-Aided Hardware Test Generation - (2024).
• LLM-aided Test Generation for Custom Neural Network Hardware Accelerators - (2025).
• Llm-tg: Towards automated test case generation for processors using large language models - (2024).
• RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation - (2026).
• Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generation - (2026).
• Saarthi: The First AI Formal Verification Engineer - (2025).
• SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine - (2025).
• Semantic-Guided Test Generation using Fine-Tuned LLMs for Validation of Hardware Accelerators - (2026).
• SHARP: A Comprehensive SystemC HLS Benchmark Suite and LLM-Assisted Testbench Optimization for RTL Coverage Closure - (2026).
• Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization - (2025).
• SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation - (2026).
• SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop - (2026).
• Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging - (2026).
• Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation - (2026).
• SVVHD: An Open-Source and Self-Verified Benchmark Framework for LLM Evaluation in VHDL Code Generation - (2026).
• The Simulation Semantics of Synthesisable Verilog - (2025).
• Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis - (2026).
• UCAgent: An End-to-End Agent for Block-Level Functional Verification - (2026).
• Understanding Language Model Capabilities in Formal Verification of Digital Hardware - (2024).
• Using Large Language Models for Hardware Test Stimuli Generation - (2023).
• Using LLMs to Facilitate Formal Verification of RTL - (2023).
• Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation - (2026).
• VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation - (2025).

🐛 Bug Fixing & Debug

• A Retrieval-Augmented Framework for Automated RTL Testability Repair - (2025).
• A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction - (2025).
• ARSP: Automated Repair of Verilog Designs via Semantic Partitioning - (2025).
• Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks - (2026).
• Explaining EDA synthesis errors with LLMs - (2024).
• High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair - (2024).
• LLM-Powered EDA Log Analysis for Effective Design Debugging - (2025).
• LLMs And Static Hardware Analysis for Early Detection of RTL Bugs - (2025).
• Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging - (2025).
• Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learning - (2025).
• Re-thinking RTL Debug Automation using LLMs - (2024).
• Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generation - (2025).
• SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation - (2026).
• Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection - (2024).
• Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph - (2025).
• Timing Violation-Aware Debugging of RTL Code using Large Language Models - (2025).
• Understanding and Mitigating Errors of LLM-Generated RTL Code - (2025).

🏗️ Back-end Design

🔀 Logic Synthesis

• A Multi-Task Learning Approach for Logic Synthesis Optimization - (2024).
• LLSM: LLM-enhanced logic synthesis model with EDA-guided CoT prompting, hybrid embedding and AIG-tailored acceleration - (2025).
• Verified RTL Synthesis at Scale - (2026).

📐 Physical Design & PPA

• Agentic AI for Physical Design R&D: Status and Prospects - (2026).
• An Intelligent Integrated Circuit Backend Design Framework Using Open EDA - (2024).
• An Open-Source Intelligent Physical Implementation Toolkit and Library - (2023).
• Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning - (2026).
• Automated QoR improvement in OpenROAD with coding agents - (2026).
• Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms - (2024).
• Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing - (2026).
• Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts - (2025).
• Evolution of Optimization Algorithms for Global Placement via Large Language Models - (2025).
• Evolving Macro Placements with Vision-Language Models - (2026).
• Focus session: Large language models in physical design: From data generation to intelligent agents - (2026).
• GR-Evolve: Design-Adaptive Global Routing via LLM-Driven Algorithm Evolution - (2026).
• Multimodal Chip Physical Design Engineer Assistant - (2025).
• PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design - (2026).
• Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimization - (2026).

🌐 Domains

📡 Analog & Mixed-Signal

• A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits - (2025).
• Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing - (2025).
• AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design - (2026).
• AMSnet 2.0: A larger AMS database with AI Segmentation for Net Detection - (2025).
• AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits - (2026).
• Amsnet: Netlist dataset for ams circuits - (2024).
• An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design - (2024).
• Analog Circuit Design via Training-Free Code Generation - (2024).
• Analogagent: Self-improving analog circuit design automation with llm agents - (2026).
• Automated Extraction and Design of Analog Circuits from Documents with Large Language Model - (2024).
• AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents - (2026).
• CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt - (2026).
• DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams - (2026).
• EDAForge: A Multi-Agent Orchestration Framework for Autonomous Analog Circuit Synthesis - (2026).
• EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit - (2025).
• Emerging ML-AI Techniques for Analog and RF EDA - (2025).
• Evaluating LLM-based Workflows for Switched-Mode Power Supply Design - (2025).
• Exploring large language models for verilog hardware design generation - (2024).
• From Prompt to Accelerator: A Perspective on LLM-Based Analog In-Memory Accelerator Design Automation - (2025).
• Graph Neural Networks Based Analog Circuit Link Prediction - (2025).
• Large Language Model-based Automated Analog IC Design Framework from Image to Layout - (2026).
• LATENT: LLM-Augmented Trojan Insertion and Evaluation Framework for Analog Netlist Topologies - (2025).
• Leveraging LLMs for Dataset Creation via Automated SPICE Netlist Extraction from Analog Circuit Diagrams - (2024).
• Limca: Llm for automating analog in-memory computing architecture design exploration - (2026).
• LLM Agents for Analog Integrated Circuit Design: A Taxonomy and a Retrieval-Augmented Prototype - (2026).
• LLM-based AI Agent for Sizing of Analog and Mixed Signal Circuit - (2025).
• MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design - (2025).
• Multimodal-LLM Based AI Agent for Schematic Generation of Analog Circuit - (2025).
• RFAmpDesigner: A Self-Evolving Multi-Agent LLM Framework for Automated Radio Frequency Amplifier Design - (2026).
• Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design - (2025).
• TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits - (2025).
• VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing - (2026).

🧩 FPGA

• A Dataset for LLM-Based Detection of Power-Wasters in Routed FPGA Netlists - (2025).
• Benchmarking LLM-Generated FPGA Designs with Resource Awareness - (2025).
• Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis - (2024).
• Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference - (2026).
• LLM-based Agents for Accelerated FPGA Design - (2026).
• LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization - (2025).
• LLM-Driven Design Space Exploration of FPGA-based Accelerators - (2026).

🔒 Hardware Security

• A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion - (2026).
• A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection - (2026).
• AI-Assisted Hardware Security Verification - (2026).
• Automation of LLM Self-Instructing for Hardware Security Verification - (2024).
• Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking - (2026).
• Evaluating Pre-trained LLMs to Detect and Localize Hardware Trojans - (2024).
• Evolutionary Large Language Models for Hardware Security - (2024).
• Fixing Hardware Security Bugs with Large Language Models - (2023).
• HardSecBench: Benchmarking the Security Awareness of LLMs for Hardware Code Generation - (2026).
• Hardware Vulnerability Discovery using an LLM-Assisted Hybrid Platform for Zero-Shot Knowledge Extraction and Refinement - (2025).
• Harnessing the Power of LLMs for Enhancing Hardware Security - (2026).
• LATENT: LLM-Augmented Trojan Insertion and Evaluation Framework for Analog Netlist Topologies - (2025).
• LLM-based Framework for RTL Trojan Localization - (2025).
• LLMPirate: LLMs for Black-box Hardware IP Piracy - (2024).
• LLMs for Secure Hardware Design and Related Problems - (2026).
• Rtl-breaker: Assessing the security of llms against backdoor attacks on hdl code generation - (2025).
• Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection - (2024).
• Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design - (2025).
• VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog - (2026).
• VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding - (2025).

⚡ AI Accelerator & Architecture

• A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference - (2024).
• AI-on-Chip Systems: A Cross-Layer Review of Architectures, Interconnects, Design Automation, and Embedded Intelligence - (2026).
• Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference - (2026).
• Chat-A2: An LLM-aided Design Space Exploration Framework for High-Performance CPU Design - (2026).
• Designing Efficient LLM Accelerators for Edge Devices - (2024).
• Exploring Efficient Wafer-Scale Chip Design for Large Language Models - (2024).
• Forecasting LLM Inference Performance via Hardware-Agnostic Analytical Modeling - (2025).
• Generative AI through CAS lens: An integrated overview of algorithmic optimizations, architectural advances, and automated designs - (2025).
• MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation - (2025).
• Powering the AI Supercycle: Design for AI and AI for Design - (2026).
• QiMeng: fully automated hardware and software design for processor chip - (2025).
• TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator - (2025).

🏛️ Foundations & Infrastructure

🧠 Foundation Models

• A Benchmark on Directed Graph Representation Learning in Hardware Designs - (2024).
• A LoRA Fine-Tuned LLM Model for Efficient Automated Assertion Generation - (2025).
• A survey of circuit foundation model: Foundation ai models for vlsi circuit design and eda - (2025).
• An Iterative Framework for Fine-tuning LLMs for RTL Code Generation - (2024).
• Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning - (2025).
• BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks - (2025).
• ChipLingo: A Systematic Training Framework for Large Language Models in EDA - (2026).
• Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors - (2025).
• DeepRTL2: A Versatile Model for RTL-Related Tasks - (2025).
• DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model - (2025).
• FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design - (2025).
• Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique - (2023).
• GPT-4 Technical Report - (2023).
• InCoder-32B: Code Foundation Model for Industrial Scenarios - (2026).
• LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning - (2025).
• NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph - (2025).
• ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model - (2025).
• Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation - (2025).
• ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation - (2025).
• The Representation Bottleneck in LLM Hardware Design - (2026).
• Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL - (2026).

🗂️ Benchmarks & Datasets

• A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - (2024).
• A Benchmark for Verilog Code Metric Reasoning Using LLMs - (2024).
• A Benchmark on Directed Graph Representation Learning in Hardware Designs - (2024).
• A Large Language Model Dataset for Enhanced Interaction with OpenROAD - (2024).
• A New Benchmark for the Appropriate Evaluation of RTL Code Optimization - (2026).
• Assessing LLM-Driven Verilog Coding for Data Contamination - (2025).
• Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms - (2024).
• Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing - (2026).
• CktEvo: Repository-Level RTL Code Benchmark for Design Evolution - (2026).
• Evaluating Creativity of LLM-Based Hardware Code Generation - (2024).
• Evaluating LLM-based Workflows for Switched-Mode Power Supply Design - (2025).
• Evaluating LLMs for Hardware Design and Test - (2024).
• Fixme: Towards end-to-end benchmarking of llm-aided design verification - (2026).
• GenBen: A Genarative Benchmark for LLM-Aided Design - (2025).
• Graph Neural Networks Based Analog Circuit Link Prediction - (2025).
• Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench - (2026).
• MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs - (2025).
• NotSoTiny: A Large, Living Benchmark for RTL Code Generation - (2025).
• Prompting for Power: Benchmarking Large Language Models for Low-Power RTL Design Generation - (2025).
• PyraNet: A Multi-Layered Hierarchical Dataset for Verilog - (2024).
• RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models - (2026).
• RTLBench: A Multi-Dimensional Benchmark Suite for Evaluating LLM-Generated RTL Code - (2025).
• RuC: HDL-Agnostic Rule Completion Benchmark Generation - (2026).
• SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design - (2025).
• VerifLLMBench: An Open-Source Benchmark for Testbenches Generated with Large Language Models - (2025).
• VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation - (2024).

🛠️ Techniques (RAG/RL/Prompt/FT)

• A Custom RAG-based Conversational Assistant for OpenROAD - (2024).
• A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base - (2025).
• A Retrieval-Augmented Framework for Automated RTL Testability Repair - (2025).
• A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection - (2026).
• An Iterative Framework for Fine-tuning LLMs for RTL Code Generation - (2024).
• AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation - (2025).
• Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting - (2024).
• Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning - (2026).
• Can Low-Rank Knowledge Distillation in LLMs be Useful for Microelectronic Reasoning? - (2024).
• ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation - (2026).
• CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt - (2026).
• CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts - (2026).
• Controlled Verilog Generation with Discriminative Guidance - (2024).
• CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation - (2024).
• CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference - (2025).
• Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation - (2025).
• CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations - (2026).
• CPPL: A Circuit Prompt Programming Language - (2026).
• Finetuning LLMs for Chip Design via an Automated design-data augmentation framework - (2024).
• From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation - (2026).
• From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis - (2026).
• Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning - (2025).
• Graph Neural Networks Based Analog Circuit Link Prediction - (2025).
• Hierarchical Prompting for LLM-based Chip Design - (2024).
• Improving LLM-Powered EDA Assistants with RAFT - (2025).
• Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification - (2026).
• Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning - (2024).
• Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap - (2024).
• Leveraging LLMs for Dataset Creation via Automated SPICE Netlist Extraction from Analog Circuit Diagrams - (2024).
• LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning - (2025).
• Non-Overlapping Placement of Macro Cells based on Reinforcement Learning in Chip Design - (2024).
• Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models - (2024).
• Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learning - (2025).
• RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS): A Structured Methodology Using Large Language Models for Hardware Design - (2026).
• Reinforcement Learning with Human Feedback - (2023).
• Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation - (2025).
• ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards - (2025).
• Speculative Decoding for Verilog: Speed and Quality, All in One - (2025).
• TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog - (2026).
• VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation - (2026).
• VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation - (2025).

🤖 Multi-Agent Systems

• A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization - (2025).
• A Multi-Agent Generative AI Framework for IC Module-Level Verification Automation - (2025).
• A Next-Generation Benchmark Dataset for Evaluating LLMs and Agents on RTL Design and Verification - (2025).
• A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection - (2026).
• A Survey of Autonomous Digital Chip Design - (2025).
• Agentic Chip Design from Spec2GDS-Faster and Better than a Human Expert? - (2026).
• Agentic Electronic Design Automation: A Handoff Perspective - (2026).
• Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric - (2025).
• Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing - (2025).
• AI Agents for Photonic Integrated Circuit Design Automation - (2025).
• AiEDA: Agentic AI design framework for digital ASIC system design - (2024).
• An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation - (2025).
• An Efficient Program Generation Multi-Agent System for Automatic RTL Verification - (2025).
• An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design - (2024).
• AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testing - (2025).
• Automated Multi-Agent Workflows for RTL Design - (2025).
• Autonomous Verilog Coding Agents with Graph-based Planning and AST-based Waveform Tracing - (2024).
• ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration - (2026).
• ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation - (2026).
• CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts - (2026).
• Closing the Loop: Overcoming the Tool-Feedback Gap in Agentic Hardware Design - (2026).
• Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair - (2026).
• CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization - (2026).
• CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation - (2024).
• Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement - (2026).
• DUET: Agentic Design Understanding via Experimentation and Testing - (2025).
• Enabling EDA Flow Automation through Microservice-Based LLM Agents - (2025).
• Exploring the Agentic Frontier of Verilog Code Generation - (2026).
• Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs - (2024).
• HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation - (2026).
• Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification - (2025).
• JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation - (2025).
• LayoutCopilot: an LLM-powered multiagent collaborative framework for interactive analog layout design - (2025).
• LLM Agents as Catalysts for Resilient DFT: An Orchestration-Based Framework Beyond Brittle Scripts - (2025).
• LLM Agents for Chip QoR Optimization - (2026).
• LLM-based Multi-Agent Collaboration System for Electronic Design Automation - (2025).
• MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA - (2026).
• MAGE: A Multi-Agent Engine for Automated RTL Code Generation - (2024).
• Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design - (2025).
• MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization - (2025).
• MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design - (2025).
• Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging - (2025).
• OpenROAD Agent: An Intelligent Self-Correcting Script Generator for OpenROAD - (2025).
• Prompt, Fab, Flex: Agentic LLMs for Flexible Electronics Design - (2025).
• Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generation - (2025).
• RTLSquad: Multi-Agent Based Interpretable RTL Design - (2025).
• SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation - (2026).
• Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems - (2025).
• Tool-Using Agents for Chip Design Optimization - (2025).
• Towards LLM4Floorplan: Agents Can Do What Engineers Do in Chip Design - (2024).
• Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence - (2025).
• Using GUI Agent for Electronic Design Automation - (2025).
• Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation - (2026).
• VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation - (2026).
• VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs - (2026).
• VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing - (2026).

🛰️ EDA Tools & Copilots

• A flexible language model-assisted electronic design automation framework - (2026).
• A Large Language Model Dataset for Enhanced Interaction with OpenROAD - (2024).
• AI-Assisted IC Design With Accelerated Computing and LLM-Driven Optimization: Toward Faster, Smarter Electronic Design Automation - (2026).
• Artificial Intelligence-Assisted IC Design: Large language models and agentic systems for modern chip design - (2026).
• Autonomous Evolution of EDA Tools - (2026).
• Bottom-Up Generation of Verilog Designs for Testing EDA Tools - (2025).
• ChipMate: Design-experience-driven chip recommendation framework based on multi-agent collaboration - (2026).
• Electronic Design Automation for Superconducting Quantum Chip - (2025).
• Leveraging Large Language Models and AI Agents for Enhanced Chip Design Automation - (2026).
• LLM-Aided Efficient Hardware Design Automation - (2024).
• LLM-aided interface for Open Source Chip Design - (2026).
• New interaction paradigm for complex eda software leveraging gpt - (2023).
• Towards a ML-Assisted EDA Tools - (2025).

📚 Surveys & Reviews

📚 Surveys & Reviews

• A critical review and evaluation of LLMs for RTL generation - (2026).
• A Survey of GPT-3 Family Large Language Models Including ChatGPT and GPT-4 - (2023).
• A Survey of Research in Large Language Models for Electronic Design Automation - (2025).
• Challenges and Opportunities in Conversational Hardware Design - (2023).
• Emerging Progress in Large Language Models for Electronic Design Automation - (2024).
• Enhancing Electronic Design Automation With Large Language Models: A Taxonomy, Analysis and Opportunities - (2026).
• Exploring Generation and Review of VLSI Design Specification with Large Language Model - (2024).
• Hardware Design and Security Needs Attention: From Survey to Path Forward - (2025).
• Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective - (2026).
• Large Language Models (LLMs) for Electronic Design Automation (EDA) Special Session Paper - (2025).
• Large language models for eda: Future or mirage? - (2025).
• LLM-Assisted Circuit Verification: A Comprehensive Survey - (2026).
• Llms and the future of chip design: Unveiling security risks and building trust - (2024).
• Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD - (2024).
• Report for NSF Workshop on AI for Electronic Design Automation - (2026).
• Revolution or Hype? Seeking the Limits of Large Models in Hardware Design - (2025).
• Summary of ChatGPT-Related Research and Perspective Towards the Future of Large Language Models - (2023).
• The dawn of ai-native eda: Opportunities and challenges of large circuit models - (2024).
• The potential of llms in hardware design - (2024).
• Towards better chip design via AI-driven approaches - (2025).

Contributing

Contributions are welcome! The easiest way is to open an ["Add a paper" issue] — no git knowledge needed. To edit directly, add a line under the right section in this README for the format and inclusion criteria).

Data Provenance & Disclaimer

• The list was seeded with 342 trusted entries curated from a community spreadsheet of LLM-for-EDA literature (2023–2026). Fifty additional candidate rows were excluded at import because the original collector flagged them as unverified.

• arXiv links are canonicalized to stable abs/ URLs. Categories were normalized — legacy tags and arXiv subject classes (e.g. cs.AR) were mapped to the buckets above.

• 335 entries currently carry Summary TBD. — these are the community's first targets.

• 7 entries could not be confidently categorized and are held back until triage; they are not shown above.

• Inclusion is not endorsement. Please verify any paper against its primary source before relying on it.

License

CC0-1.0 — released to the public domain.