A collection of reusable Clash designs/examples.
See here and here for projects built using components in this library.
Each design has a Hspec testsuite/specification in the /tests subdirectory. A handful of designs have formal properties in the /formal directory.
FPGA proven designs are indicated in the module documentation.
Haskell
98.2%
SystemVerilog
1.4%
A collection of reusable Clash designs/examples.
See here and here for projects built using components in this library.
Each design has a Hspec testsuite/specification in the /tests subdirectory. A handful of designs have formal properties in the /formal directory.
FPGA proven designs are indicated in the module documentation.
Haskell
98.2%
SystemVerilog
1.4%