Solar FemtoTX Landing Page for Project, Status & Updates

http://ei2030.github.io/FemtoTX

2-3-2026

Several pull requests have been merged https://github.com/srvedulageth/solar_femtoTx/pull/4

2-2-2026

Vedula got DDR3 pings completed! Zero packet loss & 100% pings worked!

1-20-2026

Vedula says, "I am able to get simulation working with DRAM and testing on emulation."

1-16-2026

Vedula has designed a bridge to connect Wishbone and Application interface.

11-26-2025

Vedula has reported pings work, while timeouts occur. As of 12-3, he is currently debugging.

11-05-2025

Vedula has completed TX and RX continuous testing!

https://github.com/user-attachments/assets/7d4f2f48-4a5c-43dc-9d0d-9d9809e34246

https://youtu.be/E1b18wrB_ZA

Next up: validation on FPGA of full duplex.

10-25-2025

Vedula has completed EthMac Tx. He sent data from the ZAP SoC to his Windows desktop and captured the Tx using Wireshark. He will test Rx now and then work on booting linux.

9-6-25

VS reports:

1. Checked in code with EthMAC integrated.
2. Implemented SoC with Ethmac. No errors and able to transfer on uart.
3. Next Task Write Driver for EthMAC.

8-24-25

the ZAP core has cache:

https://en.wikipedia.org/wiki/Transistor_count#Microprocessors

https://www.techrxiv.org/users/814616/articles/1270555-a-heuristic-method-for-designing-solar-circuits Estimating the power consumption can be tricky. At 130nm, 22nm, and 3nm. The budget of this project will allow 130nm, but it's unclear how much funding would be needed for 22nm, and eDRAM

https://www.musesemi.com/full-block-tapeout-pricing https://www.cmc.ca/globalfoundries-22fdx-fdsoi-22-nm/ https://www.src.org/calendar/e003676/barth.pdf

8-13-25

Vedula has completed synthesis and loading of the FPGA with UART & ZAP Core. He made an LED test, which shows 3 continuously lit LEDs, and one blinking. He connected UART Tx (output from ZAP SoC), and whenever he presses a key, the LED comes back as it was connected to tx_0, which is the blinking LED.

https://github.com/user-attachments/assets/a891d421-b59e-4ba2-997c-f307857429f3

This step was an intermediate stage before he can begin booting linux, which he will work on next.

7-22-25

https://www.allaboutcircuits.com/ip-cores/all/P720/ Other ISAs that may be of use/complement ZAP core

https://github.com/stnolting/neorv32

https://www.allaboutcircuits.com/ip-cores/processor/

https://www.allaboutcircuits.com/ip-cores/processor/arm4u/ https://github.com/freecores/arm4u

https://www.allaboutcircuits.com/ip-cores/processor/aor3000/ https://github.com/alfikpl/aoR3000

https://www.allaboutcircuits.com/ip-cores/processor/mips-enhanced/

https://opencores.org/projects/mips789

https://github.com/freecores/mips789/tree/master/core

7-21-25

See paper for background and candidate cores.

FA526: https://www.innopower-tech.com/html/products/functional/FA5.jsp

7-18-2025

Current Milestone 3: Simulating Linux

Vedula is working on implementing the ZAP SoC on the FPGA Arty xc7a100tcsg324. A Storm Core (ARM7) has been found to be completely implemented in an FPGA w/ Altera, therefore we may switch to that core, add EthMac, and implement that one instead.

6-17-2025

Vedula says:

1. I just created a tag, solar_femtoTX_Milestone-1

A very very basic EthMAC access test i put in.

1. SoC has ZAP core + EthMAC + UART(2 Instances) + Timer(2 Instances) + VIC(1 Instance)
2. Synthesized SoC for Xilinx xc7a100tcsg324-1.
3. Test bench is up with these modules. Ran few tests.

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Synthesis performed on an ARTY A7 (Artix-A7) 100T

6-06-2025 Update

The Ethernet controller will be using the EthMac core

The FemtoTX will be similar the ARM926EJ-based SAM9x60 and NU980 boards by Microchip and Nuvoton

https://github.com/EI2030/Low-power-E-Paper-OS/blob/master/Hyperlinks.md#arm9-armv5-socs

06-02-2025

Vedula has completed synthesis of a ZAP processor on an Artix A7!:

Github repository

Vedula's notes:

"Please see Save/ dir for Synthesis report.

Added a separate Readme for convenience."

https://github.com/srvedulageth/solar_femtoTx/blob/main/README.solar_femtoTx